Static random access memory (SRAM) is a type of RAM that uses transistor driven data cells to latch bits of data for memory storage and is used in a large variety of consumer electronics, such as computers and cellular telephones. Data cells in a SRAM circuit are typically arranged in an array, such that the SRAM includes individually addressable rows and columns to which data can be written and from which data can be read. The individually addressable rows and columns are controlled by peripheral circuitry that receives decoded signals corresponding to memory locations, which could be generated from a processor, such that the peripheral circuitry determines which of the data cells in the array are written to and read from at any given time. While data is being transferred to and from a SRAM circuit, the SRAM is considered to be in an activation mode, such that all of the data cells in the array are receiving power and are capable of freely allowing data transfer to and from the data cells.
The market for consumer electronics, however, is constantly improving. There is an increasing demand for smaller circuit packages that consume less power for the purpose of conserving battery-life, such as in wireless communication applications. One attempt to achieve lower power consumption is to switch the SRAM from an active mode to a retention mode of operation at times when data is not being written to or read from the memory array. To retain the data written into the SRAM memory array, the memory array needs a continuous power supply. In the retention mode of operation, power is continuously supplied to the SRAM, but the power supplied to the SRAM is reduced, resulting in lower power consumption in the form of leakage current. However, excess power consumption due to leakage current becomes particularly problematic as SRAM transistor gate-oxide sizes shrink (e.g., 70 nm or smaller), even when the SRAM is in the retention mode. Additionally, accessing data from a SRAM memory array that is in the retention mode impacts system performance due to the amount of time that it takes for the power to be increased to switch the SRAM to the activation mode to allow data read and write operations.